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quad-channel isolators with integrated dc-to-dc converter adum5401/adum5402/adum5403/adum5404 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features iso power integrated, isolated dc-to-dc converter regulated 3.3 v or 5.0 v output up to 500 mw output power quad dc-to-25 mbps (nrz) signal isolation channels schmitt trigger inputs 16-lead soic package with >8.0 mm creepage high temperature operation: 105c high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition 2500 v rms for 1 minute per ul1577 csa component acceptance notice #5a (pending) vde certificate of conformity (pending) din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak applications rs-232/rs-422/rs-485 transceivers industrial field bus isolation power supply startup bias and gate drives isolated sensor interfaces industrial plcs general description the adum5401/adum 5402/adum5403/adum5404 1 devices are quad-channel digital isolators with iso power?, an integrated, isolated dc-to-dc converter. based on the analog devices, inc., i coupler? technology, the dc-to-dc converter provides up to 500 mw of regulated, isolated power at either 5.0 v from a 5.0 v input supply or 3.3 v from a 3.3 v supply. this eliminates the need for a separate, isolated dc-to-dc converter in low power, isolated designs. the i coupler chip scale transformer technology is used to isolate both the logic signals and the magnetic components of the dc-to-dc converter. the result is a small form factor, total isolation solution. the adum5401/adum5402/adum5403/adum5404 isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the ordering guide for more information). iso power uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. refer to application note an-0971 for details on board layout considerations. functional block diagrams 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc rect 4 channel i coupler core v dd1 reg gnd 1 v ia /v oa v ib /v ob v ic /v oc v od rc out gnd 1 v iso gnd iso v oa /v ia v ob /v ib v oc /v ic v id v sel gnd iso adum5401/adum5402/ adum5403/adum5404 06577-001 figure 1. adum5401/adum5402/adum5403/adum5404 3 4 5 6 14 13 12 11 adum5401 06577-100 v ia v ib v oa v ob v ic v oc v od v id figure 2. adum5401 3 4 5 6 14 13 12 11 adum5402 06577-101 v ia v ib v oa v ob v oc v ic v od v id figure 3. adum5402 3 4 5 6 14 13 12 11 adum5403 06577-102 v ia v ob v oa v ib v oc v ic v od v id figure 4. adum5403 3 4 5 6 14 13 12 11 adum5404 06577-103 v oa v ob v ia v ib v oc v ic v od v id figure 5. adum5404 1 protected by u.s. patents 5,952,849; 6,873,065; 6, 903,578; and 7,075,329. other patents are pending.
adum5401/adum5402/ad um5403/adum5404 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics5 v primary input supply/ 5 v secondary isolated supply ................................................... 3 ? electrical characteristics3.3 v primary input supply/ 3.3 v secondary isolated supply ................................................ 5 ? package characteristics ............................................................... 7 ? regulatory approvals ................................................................... 7 ? insulation and safety-related specifications ............................ 7 ? din v vde v 0884-10 (vde v 0884-10) insulation characteristics .............................................................................. 8 ? recommended operating conditions ...................................... 8 ? absolute maximum ratings ............................................................ 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? truth table .................................................................................. 13 ? typical performance characteristics ........................................... 14 ? terminology .................................................................................... 16 ? applications information .............................................................. 17 ? pcb layout ................................................................................. 17 ? thermal analysis ....................................................................... 18 ? emi considerations ................................................................... 18 ? propagation delay-related parameters ................................... 18 ? dc correctness and magnetic field immunity ........................... 18 ? power consumption .................................................................. 19 ? power considerations ................................................................ 20 ? increasing available power ....................................................... 20 ? insulation lifetime ..................................................................... 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 11/08rev. 0 to rev. a changes to figure 1 and general description section ............... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 4 ............................................................................ 7 changes to table 6 and table 7 ....................................................... 8 changes to table 8 and table 9 ....................................................... 9 changes to figure 7 and table 10 ................................................. 10 changes to figure 8 and table 11 ................................................. 11 changes to figure 9 and table 12 ................................................. 12 changes to figure 10 and table 13 ............................................... 13 moved truth table section ........................................................... 13 changes to applications information section and pcb layout section .............................................................................................. 17 changes to dc correctness and magnetic field immunity section .............................................................................................. 18 changes to power considerations section ................................. 20 added increasing available power section, table 15, and table 16 ............................................................................................ 20 5/08revision 0: initial version
adum5401/adum5402/adum5403/adum5404 rev. a | page 3 of 24 specifications electrical characteristics5 v primary in put supply/5 v secondary isolated supply 4.5 v v dd1 5.5 v, v sel = v iso ; each voltage is relative to its respective ground. all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = 5.0 v, v sel = v iso . table 1. parameter symbol min typ max unit test conditions/comments dc-to-dc converter power supply setpoint v iso 4.7 5.0 5.4 v i iso = 0 ma line regulation v iso(line) 1 mv/v i iso = 50 ma, v dd1 = 4.5 v to 5.5 v load regulation v iso(load) 1 5 % i iso = 10 ma to 90 ma output ripple v iso(rip) 75 mv p-p 20 mhz bandwidth, c bo = 0.1 f || 10 f, i iso = 90 ma output noise v iso(n) 200 mv p-p c bo = 0.1 f || 10 f, i iso = 90 ma switching frequency f osc 180 mhz pulse-width modulation frequency f pwm 625 khz dc to 2 mbps data rate 1 maximum output supply current 2 i iso(max) 100 ma v iso > 4.5 v, dc to 1 mhz logic signal frequency efficiency at maximum output supply current 3 34 % i iso = 100 ma, dc to 1 mhz logic signal frequency i dd1 supply current, no v iso load i dd1(q) 19 30 ma i iso = 0 ma, dc to 1 mhz logic signal frequency i dd1 supply current, full v iso load i dd1(max) 290 ma c l = 0 pf, dc to 1 mhz logic signal frequency, v dd = 4.5 v, i iso = 100 ma 25 mbps data rate (crwz grade only) i dd1 supply current, no v iso load i dd1(d) adum5401 68 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency adum5402 71 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency adum5403 75 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency adum5404 78 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency available v iso supply current 4 i iso(load) adum5401 87 ma c l = 15 pf, 12.5 mhz logic signal frequency adum5402 85 ma c l = 15 pf, 12.5 mhz logic signal frequency adum5403 83 ma c l = 15 pf, 12.5 mhz logic signal frequency adum5404 81 ma c l = 15 pf, 12.5 mhz logic signal frequency undervoltage lockout, v dd1 , v ddl , and v iso supply positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v
adum5401/adum5402/ad um5403/adum5404 rev. a | page 4 of 24 parameter symbol min typ max unit test conditions/comments i coupler data channels i/o input currents i ia , i ib , i ic , i id ?20 +0.01 +20 a logic high input threshold v ih 0.7 v iso , 0.7 v idd1 v logic low input threshold v il 0.3 v iso , 0.3 v idd1 v logic high output voltages rc out , v oah , v obh , v och , v odh v dd1 ? 0.3, v iso ? 0.3 5.0 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5, v iso ? 0.5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages rc out , v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl ac specifications arwz grade only minimum pulse width pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 1 mbps c l = 15 pf, cmos signal levels propagation delay t phl , t plh 55 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels crwz grade only minimum pulse width pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 25 mbps c l = 15 pf, cmos signal levels propagation delay t phl , t plh 45 60 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | pwd 6 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels t pskcd 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing directional channels t pskod 15 ns c l = 15 pf, cmos signal levels for all models output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output |cm h | 25 35 kv/s v ix = v dd or v iso , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 the contributions of supply current values for all four channels are combined at identical data rates. 2 the v iso supply current is available for external use when all data rates are below 2 mbps. at data rates above 2 mbps, the data i/o ch annels draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate c an be calculated as described in the section. the dynamic i/o channel load must be treated as an external load and included in the v iso power budget. power consumption onsumption 3 the power demands of the quiescent operation of the data channels cannot be separated from the power supply section. efficienc y includes the quiescent power consumed by the i/o channels as part of the internal power consumption. 4 this current is available for driving external loads at the v iso pin. all channels are simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dy namic load conditions. refer to the power c section for ca lculation of available current a t less than the maximum data rate.
adum5401/adum5402/adum5403/adum5404 rev. a | page 5 of 24 electrical characteristics3.3 v primary in put supply/3.3 v secondary isolated supply 3.0 v v dd1 3.6 v, v sel = gnd iso ; each voltage is relative to its respective ground. all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = 3.3 v, v iso = 3.3 v, v sel = gnd iso . table 2. parameter symbol min typ max unit test conditions/comments dc-to-dc converter power supply setpoint v iso 3.0 3.3 3.6 v i iso = 0 ma line regulation v iso(line) 1 mv/v i iso = 30 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso(load) 1 5 % i iso = 6 ma to 54 ma output ripple v iso(rip) 50 mv p-p 20 mhz bandwidth, c bo = 0.1 f || 10 f, i iso = 54 ma output noise v iso(n) 130 mv p-p c bo = 0.1 f || 10 f, i iso = 54 ma switching frequency f osc 180 mhz pulse-width modulation frequency f pwm 625 khz dc to 2 mbps data rate 1 maximum output supply current 2 i iso(max) 60 ma v iso > 3.0 v, dc to 1 mhz logic signal frequency, efficiency at maximum output supply current 3 36 % i iso = 60 ma, dc to 1 mhz logic signal frequency i dd1 supply current, no v iso load i dd1(q) 14 20 ma i iso = 0 ma, dc to 1 mhz logic signal frequency i dd1 supply current, full v iso load i dd1(max) 175 ma c l = 0 pf, dc to 1 mhz logic signal frequency, v dd = 3.0 v, i iso = 60 ma power at 25 mbps data rate 25 mbps data rate (crwz grade only) i dd1 supply current, no v iso load i dd1(d) adum5401 44 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency adum5402 46 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency adum5403 47 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency adum5404 51 ma i iso = 0 ma, c l = 15 pf, 12.5 mhz logic signal frequency available v iso supply current 4 adum5401 i iso(load) 42 ma c l = 15 pf, 12.5 mhz logic signal frequency adum5402 i iso(load) 41 ma c l = 15 pf, 12.5 mhz logic signal frequency adum5403 i iso(load) 39 ma c l = 15 pf, 12.5 mhz logic signal frequency adum5404 i iso(load) 38 ma c l = 15 pf, 12.5 mhz logic signal frequency undervoltage lockout, v dd1 ,v ddl , and v iso supply positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v
adum5401/adum5402/ad um5403/adum5404 rev. a | page 6 of 24 parameter symbol min typ max unit test conditions/comments i coupler data channels i/o input currents i ia , i ib , i ic , i id, ?10 +0.01 +10 a logic high input threshold v ih 0.7 v iso , 0.7 v idd1 v logic low input threshold v il 0.3 v iso , 0.3 v idd1 v logic high output voltages rc out , v oah , v obh , v och , v odh v dd1 ? 0.3, v iso ? 0.3 3.3 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5, v 1so ? 0.5 3.1 v i ox = ?4 ma, v ix = v ixh logic low output voltages rc out , v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl ac specifications arwz grade only minimum pulse width pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 1 mbps c l = 15 pf, cmos signal levels propagation delay t phl , t plh 60 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels crwz grade only minimum pulse width pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 25 mbps c l = 15 pf, cmos signal levels propagation delay t phl , t plh 45 60 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | pwd 6 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew t psk 45 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels t pskcd 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing directional channels t pskod 15 ns c l = 15 pf, cmos signal levels for all models output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output |cm h | 25 35 kv/s v ix = v dd or v iso , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 the contributions of supply current values for all four channels are combined at identical data rates. 2 the v iso supply current is available for external use when all data rates are below 2 mbps. at data rates above 2 mbps, the data i/o ch annels draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate c an be calculated as described in the section. the dynamic i/o channel load must be treated as an external load and included in the v iso power budget. power consumption onsumption 3 the power demands of the quiescent operation of the data channels cannot be separated from the power supply section. efficienc y includes the quiescent power consumed by the i/o channels as part of the internal power consumption. 4 this current is available for driving external loads at the v iso pin. all channels are simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dy namic load conditions. refer to the power c section for ca lculation of available current a t less than the maximum data rate.
adum5401/adum5402/adum5403/adum5404 rev. a | page 7 of 24 package characteristics table 3. parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 3 1 the device is considered a 2-terminal device: pin 1 to pin 8 are shorted together, and pin 9 to pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the sectio n for thermal model definitions. thermal analysis regulatory approvals table 4. ul csa (pending) vde (pending) recognized under the ul1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 single protection, 2500 v rms isolation voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, 400 v rms (566 v peak) maximum working voltage reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul1577, each adum5401/ad um5402/adum5403/adum5404 is proof tested by applying an insulation test voltage of 3000 v rms for 1 sec (current leakage detect ion limit = 10 a). 2 in accordance with din v vde v 0884-10, ea ch of the adum5401/adum5402/adu m5403/adum5404 is proo f tested by applying an insulat ion test voltage of 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the asterisk (*) marking bran ded on the component designates din v vde v 0884-10 approval. insulation and safety-related specifications table 5. parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap (clearance) l(i01) >8.0 mm measured from input ter minals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) >8.0 mm measured from input ter minals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 mm min distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303, part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
adum5401/adum5402/ad um5403/adum5404 rev. a | page 8 of 24 din v vde v 0884-10 (vde v 0884-10) insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by protective circuits. the asterisk (*) marking on packages denotes din v vde v 0884-10 approval. table 6. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 sec v tr 4000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 6 ) case temperature t s 150 c side 1 i dd1 current i s1 555 ma insulation resistance at t s v io = 500 v r s >10 9 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) 06577-002 figure 6. thermal derating curve, dependence of safety li miting values on case temperature, per din en 60747-5-2 recommended operat ing conditions table 7. parameter symbol min max unit operating temperature 1 t a ?40 +85 c supply voltages 2 v dd1 @ v sel = 0 v v dd1 3.0 3.6 v v dd1 @ v sel = v iso v dd1 4.5 5.5 v minimum load 3 i iso(min) 10 ma 1 operation at 105c requires redu ction of the maximum load curre nt, as specified in . table 8 2 all voltages are relative to their respective ground. 3 if the external load is less than the specified value, the power supply pwm can generate excess switching noise, potentially c ausing data integrity issues.
adum5401/adum5402/adum5403/adum5404 rev. a | page 9 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 8. parameter rating storage temperature (t st ) ?55c to +150c ambient operating temperature (t a ) ?40c to +105c supply voltages (v dd , v iso ) 1 ?0.5 v to +7.0 v v iso supply current 2 t a = ?40c to +85c 100 ma t a = ?40c to +105c 60 ma input voltage (v ia , v ib , v ic , v id , v sel ) 1, 3 ?0.5 v to v ddi + 0.5 v output voltage (rc out , v oa , v ob , v oc , v od ) 1, 3 ?0.5 v to v ddo + 0.5 v average output current per data output pin 4 ?10 ma to +10 ma common-mode transients 5 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 the v iso provides current for dc and dynamic loads on the v iso i/o channels. this current must be included when determining the total v iso supply current. for ambient temperatures between 85c and 105c, maximum allowed current is reduced. 3 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 4 see figure 6 for the maximum rated current values for various temperatures. 5 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 9. maximum continuous working vo ltage supporting 50-year minimum lifetime 1 parameter maximum unit reference standard ac voltage reinforced insulation 424 v peak all certifications unipolar ac voltage basic insulation 600 v peak working voltage per iec 60950-1 reinforced insulation 560 v peak working voltage per vde v 0884-10 dc voltage basic insulation 600 v peak working voltage per iec 60950-1 reinforced insulation 560 v peak working voltage per vde v 0884-10 1 refers to the continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more information.
adum5401/adum5402/ad um5403/adum5404 rev. a | page 10 of 24 pin configurations and function descriptions v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 gnd iso 9 adum5401 top view (not to scale) 06577-004 figure 7. adum5401 pin configuration table 10. adum5401 pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected to each other. it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the adum5401 to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each other. it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for data channels and external loads.
adum5401/adum5402/adum5403/adum5404 rev. a | page 11 of 24 v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 gnd iso 9 adum5402 top view (not to scale) 06577-005 figure 8. adum5402 pin configuration table 11. adum5402 pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected to each other. it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the adum5402 to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each other. it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for data channels and external loads.
adum5401/adum5402/ad um5403/adum5404 rev. a | page 12 of 24 v dd1 1 gnd 1 2 v ia 3 v ob 4 v iso 16 gnd iso 15 v oa 14 v ib 13 v oc 5 v ic 12 v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 gnd iso 9 adum5403 top view (not to scale) 06577-006 figure 9. adum5403 pin configuration table 12. adum5403 pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected to each other. it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ob logic output b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the adum5403 to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each other. it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ib logic input b. 14 v oa logic output a. 16 v iso secondary supply voltage output for data channels and external loads.
adum5401/adum5402/adum5403/adum5404 rev. a | page 13 of 24 v dd1 1 gnd 1 2 v oa 3 v ob 4 v iso 16 gnd iso 15 v ia 14 v ib 13 v oc 5 v ic 12 v od 6 v id 11 rc out 7 v sel 10 gnd 1 8 gnd iso 9 adum5404 top view (not to scale) 06577-007 figure 10. adum5404 pin configuration table 13. adum5404 pin function descriptions pin o. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected to each other. it is recommended that both pins be connected to a common ground. 3 v oa logic output a. 4 v ob logic output b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in of a slave iso power device to allow the adum5404 to control the regulation of the slave device. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each other. it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ib logic input b. 14 v ia logic input a. 16 v iso secondary supply voltage output for data channels and external loads. truth table table 14. truth table (positive logic) v ix input 1 v sl input v dd1 state v dd1 input (v) v is state v is utput (v) v x utput 1 otes high high powered 5.0 powered 5.0 high normal operation, data is high low high powered 5.0 powered 5.0 low normal operation, data is low high low powered 3.3 powered 3.3 high normal operation, data is high low low powered 3.3 powered 3.3 low normal operation, data is low high low powered 5.0 powered 3.3 high configuration not recommended low low powered 5.0 powered 3.3 low configuration not recommended high high powered 3.3 powered 5.0 high configuration not recommended low high powered 3.3 powered 5.0 low configuration not recommended 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d).
adum5401/adum5402/ad um5403/adum5404 rev. a | page 14 of 24 typical performance characteristics 0 5 10 15 20 25 30 35 40 0 0.02 0.04 0.06 0.08 0.10 0.12 0 6577-008 output current (a) efficiency (%) 3.3v input/3.3v output 5v input/5v output figure 11. typical power supply efficiency at 5 v input/5 v output and 3.3 v input/3.3 v output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.02 0.04 0.06 0.08 0.10 0.12 i iso (a) power dissipation (w) v dd1 = 5v, v iso = 5v v dd1 = 3.3v, v iso = 3.3v 06577-009 figure 12. typical total power dissipation vs. i iso with data channels idle 0 0.02 0.04 0.06 0.08 0.10 0.12 0 0.05 0.10 0.15 0.20 0.25 0.35 0.30 input current (a) output current (a) 06577-010 3.3v input/3.3v output 5v input/5v output figure 13. typical isolated output supply current, i iso , as a function of external load, no dynamic current draw at 5 v input/5 v output and 3.3 v input/3.3 v output 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3 .5 4.0 4 .5 5.0 5 .5 6.0 6 .5 input supply voltage (v) input cur r ent (a) power (w) i dd power 06577-011 figure 14. typical short-circuit input current and power vs. input supply voltage, v iso shorted to gnd iso 06577-012 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load figure 15. typical v iso transient load response, 5 v output, 10% to 90% load step 06577-013 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load figure 16. typical transient load response, 3 v output, 10% to 90% load step
adum5401/adum5402/adum5403/adum5404 rev. a | page 15 of 24 06577-014 bw = 20mhz (400ns/div) 5v output ripple (10mv/div) figure 17. typical v iso = 5 v output voltage ripple at 90% load 06577-015 bw = 20mhz (400ns/div) 3.3v output ripple (10mv/div) figure 18. typical v iso = 3.3 v output voltage ripple at 90% load 0 4 8 12 16 20 051 01 5 data rate (mbps) supply current (ma) 20 25 5v input/5v output 3.3v input/3.3v output 06577-016 figure 19. typical i ch supply current per forward data channel (15 pf output load) 0 4 8 12 16 20 051 01 5 data rate (mbps) supply current (ma) 20 25 5v input/5v output 3.3v input/3.3v output 06577-017 figure 20. typical i ch supply current per reverse data channel (15 pf output load) 0 5 10 15 data rate (mbps) supply current (ma) 20 25 5v 3.3v 06577-119 0 2 1 3 4 5 figure 21. typical i iso(d) dynamic supply current per input 0 1.0 0.5 1.5 2.0 2.5 3.0 0 5 10 15 data rate (mbps) supply current (ma) 20 25 5v 3.3v 06577-118 figure 22. typical i iso(d) dynamic supply current per output (15 pf output load)
adum5401/adum5402/ad um5403/adum5404 rev. a | page 16 of 24 terminology i dd1(q) i dd1(q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are oper- ating below 2 mbps, requiring no additional dynamic supply current. i dd1(q) reflects the minimum current operating condition. i dd1(d) i dd1(d) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. resistive loads on the outputs should be treated separately from the dynamic load. i dd1(max) i dd1(max) is the input current under full dynamic and v iso load conditions. t phl propagation delay t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. propagation delay skew (t psk ) t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. channel-to-channel matching channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
adum5401/adum5402/adum5403/adum5404 rev. a | page 17 of 24 applications information the dc-to-dc converter section of the adum5401/adum5402/ adum5403/adum5404 works on principles that are common to most modern power supplies. it is a secondary side controller architecture with isolated pulse-width modulation (pwm) feedback. v dd1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. power transferred to the secondary side is rectified and regulated to either 3.3 v or 5 v. the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. the adum5401/adum5402/adum5403/adum5404 provide a regulation control output (rc out ) signal that can be connected to other iso power devices. this feature allows a single regulator to control multiple power modules without contention. when auxiliary power modules are present, the v iso pins can be connected together to work as a single supply. because there is only one feedback control path, the supplies work together seamlessly. the adum5401/adum5402/adum5403/adum5404 implement undervoltage lockout (uvlo) with hysteresis on the v dd1 power input. this feature ensures that the converter does not go into oscillation due to noisy input power or slow power-on ramp rates. a minimum load current of 10 ma is recommended to ensure optimum load regulation. smaller loads can generate excess noise on chip due to short or erratic pwm pulses. excess noise generated this way can cause data corruption, in some circumstances. pcb layout the adum5401/adum5402/ad um5403/adum5404 digital isolators with 0.5 w iso power integrated dc-to-dc converters require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 23 ). note that a low esr bypass capacitor is required between pin 1 and pin 2, as close to the chip pads as possible. the power supply section of the adum5401/adum5402/ adum5403/adum5404 uses a 180 mhz oscillator frequency to efficiently pass power through its chip-scale transformers. in addition, normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. these are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 . the smaller capacitor must have a low esr; for example, use of a ceramic capacitor is advised. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. a bypass capacitor between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless both common ground pins are connected together close to the package. v dd1 gnd 1 v ia /v oa v ib /v ob v iso gnd iso v oa /v ia v ob /v ib v ic /v oc v oc /v ic v id /v od rc out v od /v id v sel gnd 1 bypass < 2mm gnd iso 06577-120 figure 23. recommended pcb layout in applications involving high common-mode transients, take care to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in table 8 , thereby leading to latch- up and/or permanent damage. the adum5401/adum5402/adum5403/adum5404 are power devices that dissipate about 1 w of power when fully loaded and running at maximum speed. because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the pcb through the gnd pins. if the devices are used at high ambient temperatures, care should be taken to provide a thermal path from the gnd pins to the pcb ground plane. the board layout in figure 23 shows enlarged pads for pin 8 and pin 9. implement large diameter vias from the pads to the ground and power planes. this reduces inductance and noise generation. multiple vias in the thermal pads can significantly reduce temperatures inside the chip. the dimensions of the expanded pads are left to the discretion of the designer and the available board space.
adum5401/adum5402/ad um5403/adum5404 rev. a | page 18 of 24 thermal analysis the adum5401/adum5402/ adum5403/adum5404 parts consist of four internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the die are treated as a thermal unit, with the highest junction tempera- ture reflected in the ja from table 3 . the value of ja is based on measurements taken with the parts mounted on a jedec standard, 4-layer board with fine width traces and still air. under normal operating conditions, the adum5401/adum5402/adum 5403/ adum5404 devices operate at full load across the full temperature range without derating the output current. however, following the recommendations in the pcb layout section decreases thermal resistance to the pcb, allowing increased thermal margins in high ambient temperatures. emi considerations the dc-to-dc converter section of the adum5401/adum5402/ adum5403/adum5404 components must operate at very high frequency to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, good rf design practices should be followed in the pcb layout. refer to the an-0971 application note, control of radiated emissions for isopower devices , for the most current pcb layout recommendations specifically for the adum5401/ adum5402/adum5403/adum5404. propagation delay-related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 24 ). the propagation delay to a logic low output may differ from the propagation delay to a logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 06577-018 figure 24. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum5401/adum5402/adum5403/ adum5404 component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum5401/ adum5402/adum5403/adum5404 components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default low state by the watchdog timer circuit. this situation should occur in the adum5401/adum5402/adum5403/adum5404 only during power-up and power-down operations. the limitation on the adum5401/adum5402/adum5403/ adum5404 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3.3 v operating condition of the adum5401/adum5402/ adum5403/adum5404 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus estab- lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d / dt )? r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). r n is the radius of the n th turn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum5401/ adum5402/adum5403/adum5404, and an imposed require- ment that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 25 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 06577-019 figure 25. maximum allowable external magnetic flux density
adum5401/adum5402/adum5403/adum5404 rev. a | page 19 of 24 for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum5401/ adum5402/adum5403/adum5404 transformers. figure 26 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 26 , the adum5401/adum5402/adum5403/adum5404 are immune and can be affected only by large currents operated at high frequency very close to the component. for the 1 mhz example, a 0.5 ka current would need to be placed 5 mm away from the adum5401/adum5402/adum5403/adum5404 to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 06577-020 figure 26. maximum allowable current for various current-to- adum5401/adum5402/adum5403/adum5404 spacings in combinations of strong magnetic field and high frequency, any loops formed by pcb traces cand induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. to avoid this, care should be taken in the layout of such traces. power consumption the v dd1 power supply input provides power to the i coupler data channels, as well as to the power converter. for this reason, the quiescent currents drawn by the data converter and the primary and secondary i/o channels cannot be determined separately. all of these quiescent power demands have been combined into the i dd1(q) current, as shown in figure 27 . the total i dd1 supply current is equal to the sum of the quiescent operating current; the dynamic current, i dd1(d) , demanded by the i/o channels; and any external i iso load. converter primary converter secondary primary data i/o 4ch i ddp(d) e secondary data i/o 4ch i iso(d) i iso i dd1(q) i dd1(d) 06577-024 figure 27. power consumption within the adum5401/adum5402/adum5403/adum5404 dynamic i/o current is consumed only when operating a channel at speeds higher than the refresh rate of f r . the dynamic current of each channel is determined by its data rate. figure 19 shows the current for a channel in the forward direction, meaning that the input is on the v dd1 side of the part. figure 20 shows the current for a channel in the reverse direction, meaning that the input is on the v iso side of the part. figure 19 and figure 20 assume a typical 15 pf load. the following relationship allows the total i dd1 current to be calculated: i dd1 = ( i iso v iso )/( e v dd1 ) + i chn ; n = 1 to 4 (1) where: i dd1 is the total supply input current. i iso is the current drawn by the secondary side external load. e is the power supply efficiency at 100 ma load from figure 11 at the v iso and v dd1 condition of interest. i chn is the current drawn by a single channel determined from figure 19 or figure 20 , depending on channel direction. the maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. i iso(load) = i iso(max) ? i iso(d)n ; n = 1 to 4 (2) where: i iso(load) is the current available to supply an external secondary side load. i iso(max) is the maximum external secondary side load current available at v iso . i iso(d)n is the dynamic load current drawn from v iso by an input or output channel, as shown in figure 21 and figure 22 . the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the additional current must be included in the analysis of i dd1 and i iso(load) .
adum5401/adum5402/ad um5403/adum5404 rev. a | page 20 of 24 power considerations the adum5401/adum5402/adum5403/adum5404 power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by uvlo circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. during application of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. when the primary side is above the uvlo threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. the outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. the primary side oscillator also begins to operate, transferring power to the secondary power circuits. the secondary v iso voltage is below its uvlo limit at this point; the regulation control signal from the secondary is not being generated. the primary side power oscillator is allowed to free run in this circum- stance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. this creates a large inrush current transient at v dd1 . when the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. the v dd1 current is reduced and is then proportional to the load current. the inrush current is less than the short-circuit current shown in figure 14 . the duration of the inrush depends on the v iso loading conditions and the current available at the v dd1 pin. as the secondary side converter begins to accept power from the primary, the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. secondary side inputs sample their state and transmit it to the primary side. outputs are valid about 1 s after the secondary side becomes active. because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required. when power is removed from v dd1 , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side hold the last state that they received from the primary side. either the uvlo level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches uvlo. increasing available power the adum5401/adum5402/ adum5403/adum5404 are designed with the capability of running in combination with other compatible iso power devices. the rc out pin allows the adum5401/adum5402/adum5403/ad um5404 to provide its pwm signal to another device acting as a master to regulate its self and slave devices. power outputs are combined in parallel while sharing output power equally. the adum5401/adum5402/ad um5403/adum5404 can only be a master/standalone, and the adum5200 can only be a slave/standalone device. the adum5000 can operate as either a master or slave. this means that the adum5000 , adum520x, and adum540x can only be used in the master slave combinations listed in table 15 . table 15. allowed combinations of iso power parts slave master adum5000 adum520x adum540x adum5000 yes yes no adum520x no no no adum540x yes yes no the allowed combinations of master and slave configured parts listed in table 15 is sufficient to make any combination of power and channel count. table 16 illustrates how iso power devices can provide many combinations of data channel count and multiples of the single unit power. table 16. configurations for power and data channels number of data channels power units 0 2 4 6 1-unit power adum5000 master adum520x master adum5401 to adum5404 master adum5401 to adum5404 master adum121x 2-unit power adum5000 master adum5000 master adum5401 to adum5404 master adum5401 to adum5404 master adum5000 slave adum520x slave adum520x slave adum520x slave 3-unit power adum5000 master adum5000 master adum5401 to adum5404 master adum5401 to adum5404 master adum5000 slave adum5000 slave adum5000 slave adum520x slave adum5000 slave adum520x slave adum5000 slave adum5000 slave
adum5401/adum5402/adum5403/adum5404 rev. a | page 21 of 24 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. analog devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the adum5401/adum5402/ adum5403/adum5404. accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined, allowing calcu- lation of the time to failure at the working voltage of interest. the values shown in table 9 summarize the peak voltages for 50 years of service life in several operating conditions. in many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. operation at working voltages higher than the service life voltage listed leads to premature insulation failure. the insulation lifetime of the adum5401/adum5402/ adum5403/adum5404 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 28 , figure 29 , and figure 30 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. a 50-year operating lifetime under the bipolar ac condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 9 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross-insulation voltage waveform that does not conform to figure 29 or figure 30 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in table 9 . 0v rated peak voltage 06577-021 figure 28. bipolar ac waveform 0v rated peak voltage 06577-023 figure 29. dc waveform notes: 1. the voltage is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0v. 0v rated peak voltage 06577-022 figure 30. unipolar ac waveform
adum5401/adum5402/ad um5403/adum5404 rev. a | page 22 of 24 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b outline dimensions 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 31. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range (c) package description package option adum5401arwz 1 , 2 3 1 1 100 40 ?40 to +105 16-lead soic_w rw-16 adum5401crwz 1 , 2 3 1 25 60 6 ?40 to +105 16-lead soic_w rw-16 adum5402arwz 1 , 2 2 2 1 100 40 ?40 to +105 16-lead soic_w rw-16 adum5402crwz 1 , 2 2 2 25 60 6 ?40 to +105 16-lead soic_w rw-16 ADUM5403ARWZ 1 , 2 1 3 1 100 40 ?40 to +105 16-lead soic_w rw-16 adum5403crwz 1 , 2 1 3 25 60 6 ?40 to +105 16-lead soic_w rw-16 adum5404arwz 1 , 2 0 4 1 100 40 ?40 to +105 16-lead soic_w rw-16 adum5404crwz 1 , 2 0 4 25 60 6 ?40 to +105 16-lead soic_w rw-16 1 tape and reel are available. the addition of an rl suffix designates a 13 (1,000 units) tape and reel option. 2 z = rohs compliant part.
adum5401/adum5402/adum5403/adum5404 rev. a | page 23 of 24 notes
adum5401/adum5402/ad um5403/adum5404 rev. a | page 24 of 24 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06577-0-11/08(a)

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